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4Mx64 SDRAM
FEATURES
53% Space Savings vs. Monolithic Solution Reduced System Inductance and Capacitance 3.3V Operating Supply Voltage Fully Synchronous to Positive Clock Edge Clock Frequencies of 133, 125 and 100MHZ Burst Operation Sequential or Interleaved Burst Length = Programmable 1, 2, 4, 8 or Full Page Burst Read and Write Multiple Burst Read and Single Write Data Mask Control Per Byte Auto and Self Refresh Automatic and Controlled Precharge Commands Suspend Mode and Power Down Mode 17mm x 23mm, 153 BGA
This product is subject to change without notice.
WED3DL644V
DESCRIPTION
The WED3DL644V is a 4Mx64 Synchronous DRAM configured as 4x1Mx64. The SDRAM BGA is constructed with four 4Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 153 lead, 17mm by 23mm, BGA. The WED3DL644V is available in clock speeds of 133MHZ, 125MHZ and 100MHZ. The range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The package and design provides performance enhancements via a 50% reduction in capacitance vs. four monolithic devices. The design includes internal ground and power planes which reduces inductance on the ground and power pins allowing for improved decoupling and a reduction in system noise.
PINOUT (TOP VIEW)
A B C D E F G H J K L M N P R T U 1 DQ41 DQ40 DQ33 DQ32 NC NC CE2# NC NC NC CE1# NC NC DQ30 DQ31 DQ22 DQ23 2 DQ43 DQ42 DQ35 DQ34 VCCQ CE3# NC CKE NC CE0# VCCQ DQ28 DQ29 DQ20 DQ21 3 DQ45 DQ44 DQ37 DQ36 VCCQ VSS VSS CAS# VSS VSS VCCQ DQ26 DQ27 DQ18 DQ19 4 DQ47 DQ46 DQ39 DQ38 VCC VCC VSS CK1 RAS# CK0 VSS VCC VCC DQ24 DQ25 DQ16 DQ17 5 NC NC NC NC VCC VCC VSS VSS WE# VSS VSS VCC VCC NC NC NC NC 6 DQ48 DQ49 DQ56 DQ57 VCC VCC VSS VSS A9 VSS VSS VCC VCC DQ06 DQ07 DQ14 DQ15 7 DQ50 DQ51 DQ58 DQ59 VCCQ VSS VSS A11 VSS VSS VCCQ DQ04 DQ05 DQ12 DQ13 8 DQ52 DQ53 DQ60 DQ61 VCCQ A4 A5 A6 A7 A8 VCCQ DQ02 DQ03 DQ10 DQ11 9 DQ54 DQ55 DQ62 DQ63 NC A3 A2 A1 A0 A10 BA1 BA0 NC DQ00 DQ01 DQ08 DQ09
PIN DESCRIPTION
A0 - A11 BA0-1 DQ0-63 CK0-1 CKE DQML0-3 DQMH0-3 RAS# CAS# WE# CE0-3# VCC VCCQ VSS Address Bus Bank Select Addresses Data Bus Clock Clock Enable Data Input/Output Masks Row Address Strobe Column Address Strobe Write Enable Chip Enables Power Supply pins, 3.3V Data Bus Power Supply, 3.3V Ground pins
DQML2 DQMH2
DQML3 DQMH3
DQMH1 DQML1
DQMH0 DQML0
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FIG. 1 4MX64 SDRAM BLOCK DIAGRAM
DQ0-63 SA0-11 BA0-1 WE# CAS# RAS# CKE CK0 CK1
WED3DL644V
A0-A11 BA0-1 WE# CAS# RAS# CE# CKE CK DQ0-15
U1
CE0#
1M x 16 x 4
DQML DQMH DQML0 DQMH0
A0-A11 BA0-1 DQ16-31 WE# CAS# RAS# CE# CKE CK
U2 1M x 16 x 4
DQML DQMH DQML1 DQMH1
CE1#
A0-A11 BA0-1 DQ32-47 WE# CAS# RAS# CE# CKE CK
U3 1M x 16 x 4
DQML DQMH DQML2 DQMH2
CE2#
A0-A11 BA0-1 DQ48-63 WE# CAS# RAS# CE# CKE CK
U4 1M x 16 x 4
DQML DQMH DQML3 DQMH3
CE3#
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INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK CKE CE# RAS#, CAS# WE# BA0,BA1 Type Input Input Input Input Input Signal Pulse Level Pulse Pulse Level Polarity
WED3DL644V
A0-11, A10/AP
Input
Level
DQ Input/Output DQML0 - (DQ0-7) DQMH0 - (DQ8-15) DQML1 - (DQ16-23) DQMH1 - (DQ24-31) Input DQML2 - (DQ31-39) DQMH2 - (DQ40-47) DQML3 - (DQ48-55) DQMH3 - (DQ56-63) VCC, VSS Supply
Level
Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the Positive Edge clock. Activates the CK signal when high and deactivates the CK signal when low. By Active High deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CE# disable or enable device operation by masking or enabling all inputs except CK, Active Low CKE and DQM. When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the Active Low operation to be executed by the SDRAM. -- Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10/AP is -- low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. -- Data Input/Output are multiplexed on the same pins The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Each DQM pin controls the byte in parentheses associated with it. Power and ground.
Pulse
Mask Active High
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Symbol VCC/VCCQ VIN VOUT tOPR tSTG PD IOS Min -1.0 -1.0 -1.0 -40 -55 -- -- Max +4.6 +4.6 +4.6 +85 +125 3.0 50 Units V V V C C W mA
RECOMMENDED DC OPERATING CONDITIONS
(Voltage Referenced to: Vss = 0V) Parameter Symbol Min Typ Supply Voltage VCC/VCCQ 3.0 3.3 Input High Voltage VIH 2.0 3.0 Input Low Voltage VIL -0.3 -- VOH 2.4 -- Output High Voltage (IOH =-2mA) Output Low Voltage (IOL = 2mA) VOL ---- Input Leakage Voltage IIL -5 -- -5 -- Output Leakage Voltage IOL Max 3.6 VCC +0.3 0.8 -- 0.4 5 5 Unit V V V V V A A
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(TA = 25C, f= 1MHZ, VCC = 3.3V) Parameter Input Capacitance Input/Output Capacitance (DQ) Symbol CIN COUT Max 8 5 Unit pF pF
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VCC = +3.3V 0.3V; -55C TA +125C Parameter/Condition Supply Voltage Input High Voltage: Logic 1; All inputs (21) Input Low Voltage: Logic 0; All inputs (21) Input Leakage Current: Any input 0V VIN VCC (All other pins not under test = 0V) Input Leakage Address Current: Any input 0V VIN VCC (All other pins not under test = 0V) Output Leakage Current: I/Os are disabled; 0V VOUT VCC Output Levels: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) Symbol VCC VIH VIL II II IOZ VOH VOL Min 3 2 -0.3 -5 -20 -5 2.4 -
WED3DL644V
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
Max 3.6 VCC + 0.3 0.8 5 20 5 - 0.4 Units V V V A A A V V
IDD SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13)
VCC = +3.3V 0.3V; -55C TA 125C Parameter/Condition Operating Current: Active Mode; Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19) Standby Current: Active Mode; CKE = HIGH; CS = HIGH; All banks active after tRCD met; No accesses in progress (3, 12, 19) Operating Current: Burst Mode; Continuous burst; Read or Write; All banks active; CAS latency = 3 (3, 18, 19) Self Refresh Current: CKE - 0.2V Commercial and Industrial temperature only (27) Symbol ICC1 ICC3 ICC4 ICC7 Max 460 180 560 4 Units mA mA mA mA
BGA THERMAL RESISTANCE
Description Junction to Ambient (No Airflow) Junction to Ball Junction to Case (Top) Symbol JA JB JA Max 19.7 14.5 3.2 Unit C/W C/W C/W Notes 1 1 1
Note: Refer to PBGA Thermal Resistance Correllation application note at www.wedc.com in the application notes section for modeling conditions.
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FIG.2
Mode Register Definition
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
WED3DL644V
BURST DEFINITION
Burst Length 2
11 10 9 8 7 6 5 4 3 BT 2 1 0 Mode Register (Mx)
Order of Accesses Within a Burst Starting Column Address Type = Sequential Type = Interleaved A0 0 0 A1 0 0 1 1 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4... ...Cn-1, Cn... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported
Reserved* WB Op Mode
CAS Latency
Burst Length
*Should program M11, M10 = " 0, 0" to ensure compatibility with future devices. M2 M1 M0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Burst Length M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved
4
8
M3 0 1
Burst Type Sequential Interleaved
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
Full Page (y)
n = A0 - A9/8/7 (location 0-y)
M8 0 -
M7 0 -
M6-M0 Defined -
Operating Mode Standard Operation All other states reserved
M9 0 1
Write Burst Mode
Programmed Burst Length
Single Location Access
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SDRAM AC CHARACTERISTICS
Parameter Clock Cycle Time1 Clock to valid Output delay1,2 Output Data Hold Time2 Clock HIGH Pulse Width3 Clock LOW Pulse Width3 Input Setup Time3 Input Hold Time3 CK to Output Low-Z2 CK to Output High-Z Row Active to Row Active Delay4 RAS# to CAS# Delay4 Row Precharge Time4 Row Active Time4 Row Cycle Time - Operation4 Row Cycle Time - Auto Refresh4,8 Last Data in to New Column Address Delay5 Last Data in to Row Precharge5 Last Data in to Burst Stop5 Column Address to Column Address Delay6 Data Out to High Impedance from Precharge CL3 CL2 CL = 3 CL = 2 Symbol tCC tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD tROH tROH 133MHZ Min 7 7.5 2 2.5 2.5 2 1 1.0 5.4 14 15 15 37 60 66 1 2 1 1.0 3 2 20 20 20 50 70 70 1 2 1 1.0 3 2 Max 1000 1000 5.4 125MHZ Min 8 10 2 2.75 2.75 2 1 1 6 20 20 20 50 80 80 1 2 1 1.5 3 2 Max 1000 1000 6
WED3DL644V
100MHZ Min 10 12 2 3 3 2 1 1.5 7 Max 1000 1000 7
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CK CK CK CK CK
120,000
120,000
120,000
NOTES: 1. Parameters depend on programmed CAS# latency. 2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If tRISE of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self-refresh exit
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COMMAND TRUTH TABLE
CKE Function Register Refresh Precharge Mode Register Set Auto Refresh (CBR) Entry Self Refresh Single Bank Precharge Precharge all Banks Previous Cycle H H H H H H H H H H H H H L H H X X Current Cycle X H L X X X X X X X X X X X X X L H CE# L L L L L L L L L L L L H X X X H H RAS# L L L L L L H H H H H H X X X X X X CAS# L L L H H H L L L L H H X X X X X X WE# L H H L L H L L L H L H X X X X X X DQM X X X X X X X X X X X X X X L H X X BA0-1
WED3DL644V
A10/AP A9-0
A11
Notes
Bank Activate Write Write with Auto Precharge Read Read with Auto Precharge Burst Termination No Operation Device Deselect Clock Suspend/Standby Mode Data Write/Output Disable Data Mask/Output Disable Power Down Mode Entry Exit
X X BA X BA BA BA BA BA X X X X X X X X
OP CODE X X X X L X H X Row Address L Column H Column L Column H Column X X X X X X X X X X X X X X X X
2
3 4 4 5 5
NOTES: 1. All of the SDRAM operations are defined by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock. 2. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 3. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 4. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 5. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations, therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
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CLOCK ENABLE (CKE) TRUTH TABLE
CKE Current State Previous Current Cycle Cycle H X L H L H L H L H L H L L H X L H L H H X H H H H H H H H H H H L H L H L H L H H L X H Any State other than listed above H L L H L H L CE# X H L L L L X X H L L H L L L L H L L L L X X X X X Command RAS# CAS# X X H H H L X X X X H X H L L L X H L L L X X X X X X X H H L X X X X X L X X H L L X X H L L X X X X X WE# X X H L X X X X X X L X X X H L X X X H L X X X X X BA0-1 X X X X X X X X X X X A10-11 X X X X X X X X X X
WED3DL644V
Action INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode exit, all banks idle ILLEGAL Maintain Power Down Mode Refer to the Idle State section of the Current State Truth Table
Notes 1 2 2 2 2 2 1 2 2 2 3
Self Refresh
Power Down
X
X OP Code
CBR Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table Entry Self Refresh
4 3 4
All Banks Idle
X OP Code X X X X X X X X X X
X
Mode Register Set Power Down Refer to the Operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
4
5
Notes: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A11-A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table.
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CURRENT STATE TRUTH TABLE
Command Current State CE# L L L L Idle L L L L H L L L L Row Active L L L L H L L L L Read L L L L H L L L L Write L L L L H L L L L Read with Auto Precharge L L L L H RAS# L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X CAS# L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X WE# L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X BA0-1 A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
WED3DL644V
Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst
Notes 2 2,3
4 2 2 5
6 2 7,8 7,8
4 8,9 8,9
4 8,9 8,9
4 4
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CURRENT STATE TRUTH TABLE (CONT.)
Command Current State CE# L L L L Write with Auto Precharge L L L L H L L L L Precharging L L L L H L L L L Row Activating L L L L H L L L L Write Recovering L L L L H L L L Write Recovering with Auto Precharge L L L L L H RAS# L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X CAS# L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X WE# L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X BA0-1 A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
WED3DL644V
Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL
Notes
4 4
4 4 4
4 4,10 4 4
4 4 9 9
4 4 4,9 4,9
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CURRENT STATE TRUTH TABLE (CONT.)
Command Current State CE# L L L L L L L L H L L L L L L L L H RAS# L L L L H H H H X L L L L H H H H X CAS# L L H H L L H H X L L H H L L H H X WE# L H L H L H L H X L H L H L H L H X BA0-1 A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
WED3DL644V
Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after trc No Operation; Idle after trc No Operation; Idle after trc Load mode register ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles
Notes
Refreshing
X X BA BA BA X X X X X BA BA BA X X X
Mode Register Accessing
Notes: 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. Both Banks must be idle otherwise it is an illegal action. 3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered. 4. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS# to CAS# Delay (tRCD) must occur before the command is given. 8. Address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
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FIG. 3 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS LATENCY=3, BURST LENGTH=1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL644V
17
18
19
CLOCK
t CC
CKE
t CH
t CL
HIGH
t RAS
CE#
t RCD
t SS
RAS#
t SH
t RCD
t SS
t SH
t RP
t SS
CAS#
t SH
t CCD
t SS
ADDR Ra
t SH
Ca
t SS
Cb
t SH
Cc Rb
Note 2
Note 2, 3
Note 2, 3
Note 2, 3 Note 4
Note 2
BA
BS
BS
BS
BS
BS
BS
A10/AP
Ra
Note 3
Note 3
Note 3
Note 4
Rb
t RAC t SAC
DQ
Qa
t SS
Db
t SH
Qc
t SLZ
WE#
t OH
t SS
t SH
t SS
DQM
t SH
Row Active
Read
Write
Read Precharge
Row Active
DON'T CARE
NOTES: 1. All input except CKE & DQM can be don't care when CE# is high at the CK high going edge. 2. Bank active & read/write are controlled by BA0~BA1.
BA0 0 0 1 1 BA1 0 1 0 1 Active & Read/Write Bank A Bank B Bank C Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP BA0 0 0 0 1 1 0 1 0 1 1 BA1 0 1 0 1 0 1 0 1 Operation Distribute auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Disable auto precharge, leave bank C active at end of burst. Disable auto precharge, leave bank D active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. Enable auto precharge, precharge bank C at end of burst. Enable auto precharge, precharge bank D at end of burst.
4.
A10/AP and BA0~BA1 control bank precharge when precharge command is asserted.
A10/AP 0 0 0 0 1 BA0 0 0 1 1 x BA1 0 1 0 1 x Precharge Bank A Bank B Bank C Bank D All Banks
August 2005 Rev. 6
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FIG. 4 POWER UP SEQUENCE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL644V
17
18
19
CLOCK
CKE
High level is necessary
CE#
t RP
RAS#
t RFC
t RFC
CAS#
ADDR
Key
RAa
BA
A10/AP
RAa
DQ
HIGH-Z
WE#
DQM
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Set Row Active (A-Bank)
DON'T CARE
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FIG. 5 READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL644V
17
18
19
CLOCK
CKE
HIGH
t RC
CE#
Note 1
t RCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
Rb
Note 3
t RAC
t SAC
Qa0
t OH
Qa1 Qa2
t SHZ Note 4
Qa3 Db0 Db1 Db2
t RDL
Db3
CL = 2 DQ
CL = 3
t RAC
Note 3
t SAC
Qa0
t OH
Qa1 Qa2
t SHZ
Qa3
Note 4
t RDL
Db0 Db1 Db2 Db3
WE#
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
August 2005 Rev. 6
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FIG. 6 PAGE READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL644V
17
18
19
CKE
HIGH
CE#
t RCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
Ra
t RDL
CL = 2 DQ CL = 3 Qa0 Qa1 Qb0 Qb1 Dc0 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1
t CDL
Dc1 Dd0 Dd1
WE#
Note 1
Note 3
DQM
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
August 2005 Rev. 6
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FIG. 7 PAGE READ CYCLE AT DIFFERENT BANK @BURST LENGTH=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL644V
17
18
19
CKE
Note 1
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
BA
A10/AP
RAa
RBb
CL = 2 DQ CL = 3
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2 QBb3
QAc0
QAc1
QBd0
QBd1 QAe0
QAe1
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0 QBd1
QAe0
QAe1
WE#
DQM
Row Active (A-Bank)
Row Active (B-Bank) Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. CE# can be don't care when RAS#, CAS# and WE# are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
August 2005 Rev. 6
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FIG. 8 PAGE WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL644V
17
18
19
CLOCK
CKE
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
BA
A10/AP
RAa
RBb
t CDL
DQ
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
t RDL
DBd1
WE#
Note 1
DQM
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank)
Write (B-Bank)
Write (A-Bank)
Write (B-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
August 2005 Rev. 6
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FIG. 9 READ & WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL644V
17
18
19
CLOCK
CKE
HIGH
CE#
RAS#
CAS#
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A10/AP
RAa
RBb
RAc
t CDL
CL = 2
DQ CL = 3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3
Note 1
QAc0
QAc1
QAc2
QAc0
QAc1
WE#
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (A-Bank)
Read (A-Bank)
DON'T CARE
NOTE: 1. tCDL should be met to complete write.
August 2005 Rev. 6
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WED3DL644V
FIG. 10 READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST LENGTH=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
HIGH
CE#
RAS#
CAS#
ADDR
Ra
Rb
Ca
Cb
BA
A10/AP
Ra
Rb
CL = 2 DQ CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
WE#
DQM
Row Active (A-Bank)
Read with Auto Precharge (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
DON'T CARE
NOTE: 1. tCDL should be controlled to meet minimum tras before internal precharge start. (in the case of Burst Length=1 & 2 and BRSW mode)
August 2005 Rev. 6
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WED3DL644V
FIG. 11 CLOCK SUSPENSION & DQM OPERATION CYCLE @CAS LATENCY=2, BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CE#
RAS#
CAS#
ADDR
Ra
Ca
Cb
Cc
BA
A10/AP
Ra
t SHZ
DQ
Qa0 Qa1 Qa2 Qa3 Qb1
t SHZ
Qb1 Dc0 Dc2
WE#
Note 1
DQM
Row Active
Read
Clock Suspension
Read
Read DQM Write
Write DQM Clock Suspension
Write DQM
DON'T CARE
NOTE: 1. DQM is needed to prevent bus contention.
August 2005 Rev. 6
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WED3DL644V
FIG. 12 READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @BURST LENGTH=FULL PAGE
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
HIGH
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
Note 3
1
1
CL = 2 DQ
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
2
2
CL = 3
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
WE#
DQM
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is same as the case of RAS# interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst stop and RAS# interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle." 3. Burst stop is valid at every burst length.
August 2005 Rev. 6
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WED3DL644V
FIG. 13 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @BURST LENGTH=FULL PAGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
t BDL
DQ
DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4
t RDL
Note 2
DAb5
WE#
DQM
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length.
August 2005 Rev. 6
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WED3DL644V
FIG. 14 BURST READ SINGLE BIT WRITE CYCLE @BURST LENGTH=2 @BURST LENGTH=FULL PAGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
Note 1
CKE
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A10/AP
RAa
RBb
RAc
CL = 2
DQ CL = 3
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
WE#
DQM
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank)
Row Active (A-Bank) Write with Auto Precharge (B-Bank)
Read (A-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
August 2005 Rev. 6
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WED3DL644V
FIG. 15 ACTIVE/PRECHARGE POWER DOWN MODE @CAS LATENCY=2, BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
t SS
CKE
Note 1 Note 3
Note 2
t SS
t SS
CE#
RAS#
CAS#
ADDR
Ra
Ca
BA
A10/AP
Ra
t SHZ
DQ
Qa0 Qa1 Qa2
WE#
DQM
Precharge Power-Down Entry
Row Active Precharge Active Power-Down Power-Down Exit Entry
Read Active Power-Down Exit
Precharge
DON'T CARE
NOTES: 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1 CK + tSS prior to Row active command. 3. Cannot violate minimum refresh specification (64ms).
August 2005 Rev. 6
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FIG. 16 SELF REFRESH ENTRY & EXIT CYCLE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL644V
17
18
19
CLOCK
t SS
CKE
Note 1
Note 2 Note 4 Note 3
t RFC min
Note 6
CE#
Note 5
RAS#
Note 7
CAS#
ADDR
BA
A10/AP
DQ
HI-Z
HI-Z
WE#
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
DON'T CARE
NOTES: TO ENTER SELF REFRESH MODE 1. CE#, RAS# & CAS# with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low." Once the device enters self refresh mode, minimum tras is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CE# starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
August 2005 Rev. 6
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FIG. 17 MODE REGISTER SET CYCLE
0 1 2 3 4 5 6 7 8
WED3DL644V
FIG. 18 AUTO REFRESH CYCLE
0 1 2 3 4 5 6 7 8 9 10
CLOCK
CKE
HIGH
HIGH
CE#
Note 2
t RFC
RAS#
Note 1
CAS#
Note 3
ADDR
Key
Ra
DQ
HI-Z
HI-Z
WE#
DQM
MRS
New Command
Auto Refresh
New Command
DON'T CARE
NOTES: Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE 1. CE#, RAS#, CAS#, & WE# activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS# activation. 3. Please refer to Mode Register Set table.
August 2005 Rev. 6
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PACKAGE DESCRIPTION
17.00 1.90 Max
WED3DL644V
23.00
0.06 0.001 10.16 3.42
20.32 1.27
1.34
.760 .050
NOTE: 1. All dimensions and tolerances conform to ASME Y14.5m 2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum. 3. Primary datum seating place is defined by the spherical crowns of the solder balls. 4. The surface finish of the package shall be EDM Charmille #24 - #27
ORDERING INFORMATION
Part Number COMMERCIAL WED3DL644V7BC WED3DL644V8BC WED3DL644V10BC INDUSTRIAL WED3DL644V7BI WED3DL644V8BI WED3DL644V10BI
August 2005 Rev. 6
Clock Frequency 133MHZ 125MHZ 100MHZ 133MHZ 125MHZ 100MHZ
Package 153 BGA 153 BGA 153 BGA 153 BGA 153 BGA 153 BGA
27
Operating Range Commercial Commercial Commercial Industrial Industrial Industrial
Temp 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C
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Document Title
4M X 64 SDRAM BGA
WED3DL644V
Revision History Rev #
Rev 1 Rev 2 Rev 3
History
Initial release Die Shrink 3.1 Updated CAP and IDD specs 3.2 Added document title page
Release Date
August 2002 May 2004 June 2004
Status
Preliminary Final Final
Rev 4 Rev 5
4.1 Changed operating temperature tOPR -40C to +85C back to commercial temp rank 0C to 70C 5.1 Changed Maximum industrial temperature on order infomation table to 85C. 5.2 Added Thermal Resistance Table
December 2004 Demember 2004
Final Final
Rev 6
6.1 Replaced operating current table with updated and corrected ICC specification
August 2005
Final
August 2005 Rev. 6
28
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